±0.25-V Class-AB CMOS Capacitance Multiplier and Precision Rectifiers

Reduction of minimum supply requirements is a crucial aspect to decrease the power consumption in VLSI systems. A high-performance capacitance multiplier able to operate with supplies as low as ±0.25 V is presented. It is based on adaptively biased class-AB current mirrors which provide high current efficiency. Measurement results of a factor 11 capacitance multiplier fabricated in 180-nm CMOS technology verify theoretical claims. Moreover, low-voltage precision rectifiers based on the same class-AB current mirrors are designed and fabricated in the same CMOS process. They generate output currents over 100 times larger than the quiescent current. Both proposed circuits have 300-nW static power dissipation when operating with ±0.25-V supplies

An Op-Amp Approach for Bandpass VGAs With Constant Bandwidth

Two approaches to implement variable gain amplifiers based on Miller op-amps are discussed. One has true constant bandwidth while the other has essentially reduced bandwidth variations with varying gain. Servo-loops and ac coupling techniques with quasi floating gate transistors are used to provide a bandpass response with very low cutoff frequency in the range of hertz. In practice, one of the schemes is shown to have bandwidth variations close to a factor two while the second one has true constant bandwidth over the gain tuning range. Experimental results of test chip prototypes in 180-nm CMOS technology verify the theoretical claims

A Highly Efficient Composite Class-AB-AB Miller Op-Amp With High Gain and Stable From 15 pF Up To Very Large Capacitive Loads

In this paper, a highly power-efficient class-AB–AB Miller op-amp is discussed. The structure uses gm enhancement based on local common-mode feedback to provide class-AB operation with enhanced effective gm , open-loop gain, unity-gain frequency, and slew rate ( SR ) without significant increase in quiescent power consumption. Utilization of a nonlinear load leads to large symmetric positive and negative SRs . Stability over an extremely wide range of capacitive loads is achieved through a combination of Miller and phase-lead compensations. The unity-gain frequency does not show sensitivity to capacitive load values. A test chip prototype fabricated in 0.18- μm CMOS technology shows 90.8-dB open-loop gain, 12.5-MHz bandwidth for a 25-pF load capacitance, and a factor 60 SR enhancement with maximum output current close to 1-mA and 43- μA total static current

An Amplified Offset Compensation Scheme and its Application in a Track and Hold Circuit.

This brief proposes a fully differential track and hold circuit using a new dc offset compensation scheme. It stores an amplified version of the offset during the hold phase, which is used in attenuated fashion during the track phase to compensate offset. This scheme is less sensitive to charge injection and other errors than conventional offset compensation schemes. Experimental results of a test chip in 0.18-μm CMOS technology verify the proposed scheme

Physical Considerations for Cherenkov Radiation Based Coincidence Time Resolution Measurements in BGO

Exploiting the Cherenkov luminescence from 511 keV photoelectric interactions is a potential solution to re-introduce BGO scintillators in time-of-flight positron emission tomography (TOF-PET). Recent improvements in vacuum- and near- ultra-violet high density (VUV- and NUV-HD) silicon photomultiplier (SiPM) technology combined with efficient data post-processing methods, make it possible to access timing information from the relatively few Cherenkov photons emitted. To achieve good coincidence time resolution (CTR) also requires low noise and fast readout electronics with small effective capacitance, which is possible by employing bootstrapping techniques.In this summary, we report the CTR evaluation of the new VUV-HD and NUV-HD enhanced SiPMs. Results using a (i) standard electronic board, and a (ii) custom designed board for timing measurements, are shown. After applying state-of-the-art correction methods, values below 400 ps CTR FWHM have been reported for 3×3 mm 2 BGO crystals with lengths ranging from 3 to 15 mm, thus indicating the excellent performance of new SiPM technology combined with our custom design board

High current efficiency classAB OTA with high open loop gain and enhanced bandwidth

An efficient class-AB OTA with enhanced output current, slew rate, open loop gain, and gain bandwidth is presented. The circuit is based on a class-AB input stage with adaptive biasing, and an output stage with dynamically biased cascode transistors. It can deliver output currents 100 times larger than the bias current with a total quiescent power dissipation of 72 µW. Measurement results of a 180 nm CMOS test chip prototype show slew rate, gain bandwidth, and open loop gain enhancement